The present invention relates generally to an output driver, and more particularly, to a low power output driver utilizing voltage lower than the supply voltage or rail voltage.
Integrated circuits which have output drivers for clock and data are known in the art. A typical prior art configuration is formed with two pairs of complementary metal oxide semiconductors (CMOS) such as the circuit depicted in FIG. 3 (e.g., an inverted CML). The CMOS can be either n-type or p-type devices. The configuration shown includes a p-type CMOS over an n-type CMOS for each CMOS pair. The n-type CMOS are not really doing anything active, as shown, but are provided for ESD protection. The supply voltage (VDD) or rail voltage is applied to the supply of the drivers and to the CMOS pairs. Each CMOS pair is connected to a pad. A series resistor RS is connected between each of the pads and a respective transmission line to “decouple” the output capacitance of the driver from the transmission line itself, i.e., it makes the impedance at the source of the transmission line more purely resistive. A termination resistor RT is connected between the junction of the series resistor RS and transmission line TL and ground to create a fixed impedance. Typically, a current mirror circuit is connected between the rail voltage and the high side of the CMOS pairs. The current mirror is driven or controlled by a reference current IREF. The power consumption of this prior art circuit is primarily determined by the current constantly being sourced through one or the other terminating resistors RT. The power can be calculated as P=V*I=VDD*(N*IREF). A typical current draw through the current mirror is on the order of 14-15 mA. With about 50 ohm terminating resistors RT, the resulting voltage drop across each terminating resistor RT is on the order of 750 millivolts (mV). Thus, the power draw, independent of the load condition, is about 50 milliwatts (mW). Since one CMOS pair or the other is always connected to one of the pads, power is constantly dissipated using the conventional circuit due to the bleeding current through the respective terminating resistor RT.
It is desirable to provide a driver output that utilizes a reduced voltage supply and has lower power consumption. It is also desirable to provide an on-chip reduced voltage power supply or regulator in combination with a plurality of low power output drivers.